1. Field of the Invention
The invention relates to a memory device, and more particularly to a memory device having a redundant memory block.
2. Description of the Related Art
FIGS. 1A and 1B are a circuit diagram and an address and data arrangement of a conventional memory device, respectively.
As shown in FIGS. 1A and 1B, a storage capacity of 1K.times.8 bits is taken as an example. In this case, 10 address lines A.sub.0 -A.sub.9 are required to address an entire main memory block (MMB) 113 via a row decoder 111 and a column decoder 112, wherein address lines A.sub.0 -A.sub.4 are electrically connected to the row decoder 111 while address lines A.sub.5 -A.sub.9 are electrically connected to the column decoder 112.
During memory device (such as random access memories (RAM)) manufacture, defects on several memory cells of memory devices can cause themselves and even the entire memory devices to function abnormally, resulting in low manufacturing yield. The more storage capacities the memory devices have, the higher density the memory devices will have. As a result, the probability of defects on memory devices is greatly increased, leading to low manufacturing yield. In order to improve manufacturing yield, a redundant memory block (RMB) is designed in each memory device. Thus, defective parts of memory cells in memory devices can be replaced with spare memory cells in the redundant memory block so as to maintain better manufacturing yield.
FIG. 2 is a circuit block diagram showing a memory device 210 having a redundant memory block 214 according to the prior art. As shown in FIG. 2, in addition to a main memory block 213, the memory device 210 includes a redundant memory block 214. The redundant memory block 214 consists of a plurality of rows of memory cells. When there are defects on parts of one row of memory cells in the main memory block 213, a spare row of memory cells in the redundant memory block 214 is used to replace the defective row of memory cells.
Referring further to FIG. 2, an address signal IA is input to access data stored in a corresponding row of memory cells of the memory device 210. At this time, if the corresponding row of memory cells is normal, it can be correctly addressed by the address signal IA via a row decoder 211 and a column decoder 212. Inversely, if the row of memory cells is abnormal, the row decoder 211 is disabled after the address signal IA is compared by an address comparator 220, and then a spare row of memory cells in the redundant memory block 214 is selected to replace the defective row of memory cells. Consequently, the memory device 210 having the redundant memory block 214 can function normally even though the main memory block 213 has local defects, thereby improving manufacturing yield.
However, the unit of the redundant memory block 214 is estimated by row. Under this circumstance, if there is only one memory cell with defect in a row of memory cells of the main memory block 213, the entire row of memory cells must be replaced with a spare row of memory cells selected from the redundant memory block 214. Therefore, the problem with how many redundant memory cells should be reserved during memory device designs is faced. Now, taking a 1K.times.8-bit memory device as an example, a row decoder can be used to address one of 32 rows of memory cells. Under the worst condition that each row of memory cells has only one defective memory cell, it is necessary to have 32 rows of redundant memory cells for replacement. As a result, the areas of the main memory block 213 and the redundant memory block 214 must have a ratio of 1:1. It is obviously unpractical.